Integrated circuits (IC) and systems on chip (SoC) are specified, designed, and modeled using a hardware descriptive language (HDL). Once complete, these HDL models are fed into a high-level synthesis system to produce a fixed data flow graph (DFG). The resulting fixed DFG is utilized by engineers to develop the hardware component. A major limitation of the current synthesis process is its inability to adjust the generated DFG to coincide with particular architectural goal such as design area, delay, latency, power, and computational precision. This novel synthesis method generates a family of DFGs, and transforms them into an architecture optimized for a particular objective.

This innovative technique is based on a canonical, compact, graph-based data structure, called Taylor Expansion Diagram (TED). The technology relies on a TED to transform the behavioral specification of the system into an architecture, optimized for a given objective (performance, area or power). This is accomplished by constructing, ordering, decomposing, and simplifying the TED diagrams.